In dynamic type-semiconductor memory devices, in order to hold data in a memory cell, there is a need to perform a refresh operation for each given period. If refresh operation is performed for memory cells in a memory cell array at a row address, for which no write operation is generated and to which no access request other than the one for refresh has not been made, the refresh operation leads to unnecessary waste of power consumption.
Among publications about the dynamic random access memory (DRAM) device for preventing such unnecessary waste of power consumption caused by the refresh operation, for reference, is JP Patent Kokai JP-P2000-113667A, for example. The above-mentioned JP Patent Kokai JP-P2000-113667A discloses a configuration in which a row register unit for a row address is provided so as to record a write operation access history, as shown in FIGS. 12 and 13, thereby canceling a refresh operation on a row address on which no write operation is executed. With this configuration, the waste of power consumption caused by the refresh operation is avoided. Referring to FIG. 12, reference numeral 1201 designates an access request unit, reference numeral 1202 designates a refresh operation generating unit, reference numeral 1203 designates a refresh counting unit, and reference numeral 1204 designates a row address buffer unit, reference numeral 1205 designates a row decoder unit, reference numeral 1206 designates the row register unit, and reference numeral 1207 designates a memory array. The access request unit 1201 receives a refresh command, a WRITE command, and a READ command when they are generated, notifies the refresh operation generating unit 1202 and the row address buffer unit 1204 of the refresh command, and notifies the row address buffer unit 1204 of the WRITE command through a line L5 and the row register unit 1206 through a line L1 of the WRITE command. The refresh operation generating unit 1202 generates the refresh operation at a time interval necessary for execution of the refresh operation so as to hold internal data in a DRAM, and notifies the refresh counting unit 1203 and the row address buffer unit 1204 of the refresh operation. The refresh counting unit 1203 stores an initial row address value for refreshing the DRAM. When a refresh request is notified, the refresh counting unit 1203 counts up the row address. When the DRAM is refreshed, the row buffer 1204 selects a row address generated by the refresh counting unit, and when the DRAM is not refreshed, the row buffer 1204 selects an external row address supplied through a line L4, and notifies the row decoder unit 1205 of the row address. The row decoder unit 1205 decodes the row address so that it is associated with a word line in the array in the DRAM, and notifies the row register unit 1206 of the decoded address, through a signal L2.
FIG. 13 is a diagram showing a configuration of the row register unit 1206 illustrated in FIG. 12. Referring to FIG. 13, reference numeral 1210 denotes a latch circuit, reference numeral 1220 denotes an AND circuit, reference numeral 1230 denotes a latch circuit data input unit, reference numeral 1240 denotes a latch circuit data output unit, and reference numeral 1250 denotes a latch circuit control signal input unit. Referring to FIGS. 12 and 13, the device described in the above-mentioned publication includes the row register unit 1206 between the row decoder unit 1205 and the memory array 1207. When a write request is made and then a write history is held at the latch circuit 1210, a logic value “1” is recorded in the latch circuit 1210. When a refresh request is made, the internal status of the latch circuit 1210 is checked. When the status indicates a logic value “0”, refresh on a row address is canceled. In other words, the output L2 of the row decoder 1205 and an output of the latch circuit 1210 are ANDed at the AND circuit 1220 of the row register unit 1206, and then a resulting output L3 is supplied to the memory array 1207.